| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 88.89 | 100.00 | 66.67 | 100.00 |
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 363908
EXPRESSION (S ? D1 : D0)
1
| -1- | Status |
|---|---|
| 0 | Covered |
| 1 | Covered |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 6 | 4 | 66.67 |
| Total Bits | 12 | 8 | 66.67 |
| Total Bits 0->1 | 6 | 4 | 66.67 |
| Total Bits 1->0 | 6 | 4 | 66.67 |
| Ports | 6 | 4 | 66.67 |
| Port Bits | 12 | 8 | 66.67 |
| Port Bits 0->1 | 6 | 4 | 66.67 |
| Port Bits 1->0 | 6 | 4 | 66.67 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| VDD | No | No | No | INPUT |
| VSS | No | No | No | INPUT |
| Z | Yes | Yes | Yes | OUTPUT |
| D0 | Yes | Yes | Yes | INPUT |
| D1 | Yes | Yes | Yes | INPUT |
| S | Yes | Yes | Yes | INPUT |
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 2 | 2 | 100.00 | |
| TERNARY | 363908 | 2 | 2 | 100.00 |
363908 assign Z = S ? D1 : D0; -1- ==> ==>
| -1- | Status |
|---|---|
| 1 | Covered |
| 0 | Covered |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |