Module Definition
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Module : dti_mux21
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 100.00 66.67 100.00

Source File(s) :
/nfs_project/gemini/DV/mahmood/all_tests_main/gemini/design/ip/dti/libs/dti_tm28hpcp_ddr4_phy/hdl/library/dti_tm28hpcp_l30_stdcells_10t_rev1p0p3.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst38.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst42.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst48.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst68.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst80.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst88.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst89.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst117.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst124.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst146.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst157.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst161.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst212.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst214.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst271.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst283.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst307.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst329.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst416.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst445.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst451.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst519.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst522.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst533.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst534.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst576.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst614.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst623.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst636.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst656.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst674.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst691.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst704.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst723.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst730.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst757.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst766.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst772.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst776.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst825.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst850.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst880.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst916.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst930.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst946.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst977.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst987.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1005.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1048.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1051.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1074.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1082.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1094.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1133.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1153.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1157.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1158.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1209.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1236.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1257.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1277.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1292.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1303.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1305.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1313.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1328.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1335.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1337.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1366.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1369.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1374.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1430.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1440.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1466.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1473.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1474.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1482.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1487.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1512.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1526.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1572.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1577.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1608.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1638.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1641.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1675.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1679.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1697.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1706.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1709.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1712.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1731.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1736.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1737.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1748.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1751.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1772.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1773.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1775.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1782.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1794.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1797.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1801.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1814.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1816.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1843.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1850.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1854.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1865.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1869.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1879.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1908.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1977.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst1999.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2003.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2005.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2008.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2016.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2018.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2027.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2127.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2139.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2144.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2145.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2176.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2180.xdti_28hc_10t_30_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2207.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2219.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2254.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2267.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2294.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2307.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2334.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2336.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2344.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2392.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2393.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2411.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2417.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2436.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2488.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2495.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2504.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2519.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2523.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2551.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2563.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2565.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2616.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2638.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2639.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2660.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2663.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2676.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2725.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2747.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2783.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2794.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2803.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2829.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2848.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2858.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2891.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2897.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2934.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2936.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2958.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst2982.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3011.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3032.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3060.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3077.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3080.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3081.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3085.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3131.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3134.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3140.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3160.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3176.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3182.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3204.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3207.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3221.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3224.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3233.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3258.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3260.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3269.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3274.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3289.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3294.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3302.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3317.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3334.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3336.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3352.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3365.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3387.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3406.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3415.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3433.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3450.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3451.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3465.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3472.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3479.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3507.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3533.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3551.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3556.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3564.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3568.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3572.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3576.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3593.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3594.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3603.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3608.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3628.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3650.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3658.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3714.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3729.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3746.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3747.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3750.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3754.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3766.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3772.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3790.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3792.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3808.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3809.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3810.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3826.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3827.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3835.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3836.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3864.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3884.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3895.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3956.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3958.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3961.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3972.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3984.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst3988.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4022.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4025.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4039.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4107.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4156.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4172.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4209.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4226.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4253.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4271.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4277.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4278.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4347.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4365.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4380.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4381.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4388.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4410.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4418.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4440.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4445.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4470.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4479.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4489.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4499.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4501.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4527.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4532.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4541.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4544.xdti_28hc_10t_30_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4574.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4642.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4701.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4707.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4713.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4722.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4745.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4752.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4756.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4799.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4800.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4809.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4846.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4847.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4848.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4849.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4856.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4858.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4892.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4915.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4956.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4964.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4965.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst4987.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5005.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5010.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5016.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5039.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5051.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5061.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5076.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5084.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5098.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5110.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5115.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5144.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5151.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5175.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5194.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5209.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5213.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5224.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5226.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5275.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5282.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5284.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5286.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5287.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5288.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5313.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5314.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5317.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5338.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5352.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5372.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5410.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5418.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5438.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5439.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5449.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5455.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5461.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5468.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5481.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5488.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5502.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5508.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5516.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5524.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5542.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5553.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5555.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5578.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5585.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5609.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5610.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5613.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5626.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5676.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5682.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5689.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5694.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5700.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5702.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5725.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5776.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5777.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5780.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5782.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5783.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5786.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5794.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5832.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5874.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5885.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5930.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst5952.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6000.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6011.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6047.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6051.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6058.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6069.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6070.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6084.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6090.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6101.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6103.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6121.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6140.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6153.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6154.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6160.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6179.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6221.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6232.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6278.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6288.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6298.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6329.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6352.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6357.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6397.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6409.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6414.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6415.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6440.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6442.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6463.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6474.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6478.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6481.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6482.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6488.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6497.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6551.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6561.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6564.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6565.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6568.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6590.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6597.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6598.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6606.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6607.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6636.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6639.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6679.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6697.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6698.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6721.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6722.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6750.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6760.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6765.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6769.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6794.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6800.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6820.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6839.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6868.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6880.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6899.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6900.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6908.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6916.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6933.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6954.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6955.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6956.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6958.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6978.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst6981.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7011.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7012.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7019.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7035.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7037.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7101.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7110.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7161.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7183.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7188.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7255.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7262.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7279.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7293.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7358.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7361.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7363.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7367.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7369.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7392.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7415.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7417.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7421.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7434.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7474.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7501.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7523.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7529.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7551.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7558.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7564.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7600.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7601.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7618.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7646.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7713.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7721.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7732.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7736.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7741.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7759.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7772.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7792.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7818.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7840.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7846.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7849.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7869.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7877.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7880.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7890.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7891.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7893.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7901.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7906.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7907.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7910.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7929.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7936.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7943.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7966.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7976.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst7994.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8012.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8029.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8039.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8042.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8050.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8063.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8067.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8077.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8087.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8115.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8124.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8125.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8152.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8164.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8165.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8179.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8180.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8190.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8196.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8206.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8210.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8211.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8216.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8221.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8246.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8273.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8280.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8282.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8284.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8292.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8295.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8304.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8329.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8332.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8376.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8377.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8390.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8394.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8427.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8437.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8445.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8450.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8453.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8473.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8492.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8502.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8509.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8522.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8553.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8558.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8562.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8565.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8567.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8597.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8601.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8624.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8626.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8627.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8639.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8658.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8692.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8698.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8700.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8706.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8709.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8716.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8732.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8735.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8759.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8800.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8801.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8876.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8888.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8891.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8895.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8916.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8924.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst8994.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9005.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9018.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9027.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9048.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9055.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9111.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9125.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9222.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9234.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9235.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9240.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9252.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9255.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9270.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9289.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9303.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9316.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9317.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9324.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9339.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9341.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9343.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9370.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9376.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9380.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9412.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9450.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9454.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9465.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9469.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9494.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9497.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9504.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9517.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9571.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9598.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9608.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9636.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9669.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9674.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9701.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9708.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9711.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9744.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9752.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9786.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9794.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9821.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9832.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9850.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9852.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9892.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9937.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9963.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst9968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10022.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10050.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10055.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10067.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10072.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10091.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10122.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10129.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10155.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10194.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10216.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10219.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10221.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10231.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10270.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10271.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10274.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10284.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10285.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10296.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10300.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10305.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10309.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10316.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10325.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10341.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10357.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10394.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10395.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10401.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10414.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10424.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10432.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10436.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10441.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10457.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10465.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10534.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10563.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10577.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10578.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10585.xdti_28hc_10t_30_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10601.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10618.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10620.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10624.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10652.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10686.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10695.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10706.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10718.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10722.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10732.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10744.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10748.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10749.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10759.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10819.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10835.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10864.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10865.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10888.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10902.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10910.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10936.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst10998.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11030.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11039.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11078.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11091.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11097.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11104.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11112.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11113.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11148.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11179.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11181.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11183.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11204.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11213.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11224.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11232.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11243.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11262.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11263.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11278.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11314.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11356.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11367.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11376.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11410.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11418.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11443.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11450.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11481.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11484.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11497.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11501.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11508.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11513.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11543.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11549.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11551.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11552.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11561.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11563.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11595.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11607.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11608.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11611.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11635.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11638.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11639.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11642.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11705.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11716.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11727.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11730.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11731.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11769.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11773.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11780.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11785.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11799.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11814.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11845.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11877.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11880.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11900.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11901.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11922.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11924.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11952.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11956.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11958.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11961.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11963.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11966.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11974.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11978.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst11997.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12001.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12004.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12015.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12019.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12051.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12068.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12078.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12095.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12117.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12165.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12167.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12179.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12195.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12243.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12248.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12267.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12270.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12284.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12286.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12296.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12313.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12317.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12348.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12359.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12360.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12361.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12376.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12390.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12393.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12400.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12409.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12417.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12443.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12451.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12459.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12478.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12504.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12505.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12511.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12531.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12533.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12552.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12562.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12565.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12581.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12583.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12584.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12591.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12597.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12620.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12623.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12637.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12645.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12674.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12682.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12740.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12745.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12823.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12856.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12858.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12859.xdti_28hc_10t_30_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12872.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12876.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12884.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12899.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12905.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12932.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12933.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12936.xdti_28hc_10t_30_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12942.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12963.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12978.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12982.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst12984.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13008.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13109.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13116.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13122.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13145.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13179.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13191.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13200.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13233.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13246.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13248.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13257.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13262.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13263.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13323.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13342.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13381.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13394.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13401.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13404.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13422.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13424.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13442.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13446.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13447.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13467.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13468.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13480.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13487.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13522.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13532.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13535.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13557.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13577.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13580.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13594.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13597.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13601.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13616.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13628.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13656.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13660.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13679.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13696.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13704.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13710.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13716.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13719.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13726.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13735.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13752.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13756.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13770.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13800.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13829.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13832.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13851.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13854.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13868.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13881.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13888.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13906.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13908.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13929.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13965.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13978.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst13985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14025.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14028.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14039.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14050.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14080.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14091.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14095.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14120.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14146.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14169.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14176.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14180.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14188.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14233.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14296.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14300.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14322.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14352.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14378.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14435.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14459.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14463.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14466.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14467.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14479.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14516.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14523.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14552.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14563.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14567.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14577.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14579.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14593.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14628.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14631.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14638.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14641.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14645.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14646.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14674.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14689.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14714.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14725.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14742.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14747.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14752.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14760.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14790.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14809.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14817.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14841.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14852.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14858.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14867.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14870.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14872.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14899.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14918.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14921.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14930.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14946.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14965.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14971.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst14998.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15008.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15019.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15041.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15054.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15081.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15097.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15107.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15113.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15114.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15131.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15153.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15169.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15190.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15193.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15212.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15218.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15273.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15277.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15291.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15305.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15332.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15354.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15371.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15373.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15388.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15392.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15401.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15412.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15415.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15426.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15436.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15474.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15477.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15480.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15496.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15530.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15531.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15536.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15548.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15556.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15578.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15607.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15617.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15618.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15629.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15661.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15690.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15694.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15705.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15709.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15745.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15760.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15763.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15779.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15786.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15792.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15794.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15802.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15810.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15885.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15891.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15893.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15900.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15915.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15969.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst15992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16000.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16028.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16047.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16055.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16091.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16092.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16098.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16106.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16122.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16157.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16164.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16222.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16246.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16252.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16283.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16299.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16347.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16357.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16369.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16373.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16392.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16401.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16420.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16454.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16505.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16530.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16546.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16558.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16570.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16572.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16580.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16585.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16589.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16602.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16645.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16646.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16674.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16684.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16695.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16699.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16700.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16710.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16747.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16756.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16763.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16774.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16775.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16810.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16846.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16850.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16857.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16871.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16885.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16891.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16914.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16934.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16949.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16976.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16991.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst16997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17019.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17029.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17046.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17049.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17051.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17055.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17058.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17060.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17066.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17067.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17104.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17111.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17127.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17135.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17144.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17146.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17155.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17157.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17158.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17171.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17177.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17190.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17202.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17207.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17210.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17211.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17213.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17216.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17228.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17249.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17283.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17289.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17329.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17334.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17341.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17342.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17359.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17362.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17364.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17365.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17371.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17422.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17445.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17475.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17488.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17496.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17502.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17545.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17546.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17553.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17568.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17594.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17641.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17649.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17661.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17667.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17670.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17673.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17684.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17688.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17695.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17698.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17737.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17751.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17760.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17771.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17778.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17790.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17802.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17831.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17837.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17854.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17857.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17869.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17874.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17885.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17905.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17936.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17948.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17967.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst17980.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18051.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18067.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18091.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18113.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18135.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18142.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18171.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18172.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18175.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18194.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18205.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18213.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18239.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18246.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18247.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18273.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18285.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18288.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18297.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18315.xdti_28hc_10t_30_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18335.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18380.xdti_28hc_10t_30_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18388.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18420.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18448.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18454.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18466.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18548.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18552.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18572.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18582.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18595.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18597.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18604.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18608.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18633.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18635.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18637.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18646.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18656.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18662.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18673.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18681.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18690.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18702.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18704.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18707.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18727.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18732.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18738.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18786.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18788.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18799.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18808.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18813.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18814.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18826.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18827.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18836.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18839.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18843.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18855.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18858.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18860.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18867.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18884.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18889.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18901.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18906.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18919.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18927.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18928.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18936.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18949.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18976.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst18992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19011.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19018.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19036.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19047.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19075.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19076.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19081.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19107.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19119.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19131.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19162.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19175.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19197.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19204.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19213.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19214.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19229.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19236.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19263.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19282.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19283.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19284.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19294.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19299.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19312.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19323.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19347.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19348.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19365.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19376.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19426.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19430.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19434.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19449.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19454.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19461.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19463.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19466.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19469.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19479.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19508.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19516.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19524.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19527.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19531.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19538.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19549.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19553.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19558.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19580.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19585.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19608.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19618.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19654.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19662.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19675.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19689.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19692.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19697.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19720.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19723.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19729.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19731.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19732.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19739.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19743.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19748.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19754.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19769.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19785.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19787.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19823.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19831.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19835.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19850.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19893.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19914.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19919.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19927.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19941.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19946.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19963.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19983.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst19987.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20011.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20018.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20036.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20039.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20043.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20058.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20078.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20095.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20146.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20156.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20160.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20173.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20186.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20196.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20203.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20204.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20220.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20224.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20234.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20263.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20284.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20306.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20311.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20319.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20320.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20326.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20344.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20367.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20394.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20399.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20420.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20473.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20480.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20489.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20496.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20508.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20541.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20553.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20560.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20565.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20566.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20575.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20579.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20590.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20595.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20604.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20700.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20729.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20736.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20738.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20747.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20751.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20752.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20759.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20786.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20800.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20813.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20823.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20833.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20834.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20851.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20854.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20869.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20884.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20902.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20915.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20982.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20988.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst20997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21026.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21067.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21069.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21072.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21103.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21137.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21143.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21151.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21154.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21183.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21192.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21193.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21201.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21225.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21262.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21305.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21325.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21347.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21348.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21416.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21438.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21453.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21459.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21463.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21472.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21504.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21527.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21553.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21561.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21564.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21569.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21664.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21679.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21694.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21712.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21720.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21722.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21732.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21736.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21739.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21747.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21759.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21769.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21817.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21844.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21888.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21904.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21908.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21917.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21930.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21944.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21952.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21960.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21963.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21978.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21993.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst21996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22011.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22047.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22054.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22080.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22089.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22094.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22112.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22124.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22125.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22146.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22161.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22176.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22189.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22222.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22224.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22262.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22298.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22300.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22323.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22325.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22367.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22391.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22423.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22427.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22459.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22474.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22518.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22541.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22552.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22556.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22566.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22576.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22594.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22604.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22611.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22623.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22639.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22660.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22662.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22671.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22682.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22692.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22713.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22722.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22727.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22738.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22754.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22760.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22778.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22779.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22790.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22801.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22806.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22807.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22812.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22821.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22829.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22830.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22869.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22874.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22881.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22903.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22914.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22942.xdti_28hc_10t_30_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22943.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22949.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22952.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22979.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22991.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22994.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst22996.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23042.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23043.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23055.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23080.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23094.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23135.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23139.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23146.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23151.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23183.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23210.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23231.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23235.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23246.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23251.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23262.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23279.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23294.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23315.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23356.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23359.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23362.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23371.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23479.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23481.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23484.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23489.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23519.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23529.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23530.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23536.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23548.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23564.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23584.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23613.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23618.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23659.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23688.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23691.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23695.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23700.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23708.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23716.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23730.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23752.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23754.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23774.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23778.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23816.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23818.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23821.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23834.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23836.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23871.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23901.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23918.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23948.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23974.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst23999.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24003.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24028.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24076.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24103.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24104.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24111.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24126.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24131.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24162.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24169.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24201.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24218.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24224.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24229.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24235.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24273.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24295.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24297.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24342.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24344.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24365.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24388.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24397.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24434.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24443.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24445.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24461.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24470.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24522.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24527.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24544.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24549.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24568.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24599.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24613.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24623.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24624.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24686.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24703.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24730.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24751.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24762.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24763.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24805.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24811.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24816.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24819.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24831.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24835.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24844.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24852.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24856.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24881.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24888.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24891.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24892.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24917.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24924.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24934.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24936.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24950.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24960.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24965.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24977.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24978.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst24990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25005.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25008.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25025.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25030.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25077.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25084.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25124.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25143.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25153.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25156.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25192.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25199.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25213.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25222.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25237.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25259.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25289.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25339.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25340.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25349.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25362.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25365.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25370.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25388.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25392.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25411.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25415.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25417.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25436.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25461.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25475.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25476.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25480.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25493.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25504.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25513.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25552.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25561.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25571.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25606.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25609.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25610.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25642.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25648.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25701.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25721.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25727.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25730.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25735.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25774.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25778.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25783.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25800.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25802.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25858.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25859.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25877.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25884.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25896.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25922.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25937.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25938.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25943.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25954.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25972.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25982.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25991.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst25994.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26005.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26030.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26038.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26069.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26092.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26096.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26111.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26135.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26139.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26146.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26203.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26207.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26214.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26231.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26233.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26249.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26282.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26284.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26307.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26309.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26316.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26336.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26371.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26377.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26388.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26436.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26451.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26480.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26484.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26508.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26533.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26575.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26585.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26591.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26606.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26607.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26609.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26625.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26707.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26708.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26718.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26730.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26759.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26784.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26788.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26801.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26802.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26804.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26814.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26822.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26844.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26856.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26915.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26919.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26928.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26936.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26941.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26957.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26970.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26973.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26974.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst26994.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27028.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27036.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27055.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27067.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27069.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27078.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27090.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27097.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27109.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27119.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27122.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27143.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27151.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27164.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27186.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27219.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27220.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27243.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27249.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27253.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27324.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27327.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27329.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27332.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27334.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27357.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27388.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27393.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27399.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27410.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27467.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27472.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27487.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27488.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27509.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27531.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27542.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27569.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27577.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27580.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27582.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27593.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27624.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27638.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27653.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27657.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27660.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27684.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27689.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27694.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27701.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27718.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27720.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27722.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27730.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27731.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27747.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27762.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27763.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27773.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27777.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27793.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27810.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27819.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27840.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27867.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27868.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27869.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27924.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27930.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27957.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27969.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27987.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27993.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27994.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst27997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28016.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28034.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28036.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28066.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28075.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28087.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28107.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28116.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28133.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28138.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28139.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28152.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28155.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28169.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28171.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28234.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28270.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28277.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28284.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28313.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28317.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28321.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28324.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28330.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28342.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28350.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28362.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28371.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28388.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28397.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28400.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28409.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28422.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28438.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28454.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28460.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28473.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28474.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28502.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28507.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28511.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28526.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28536.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28542.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28556.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28563.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28568.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28577.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28602.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28609.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28613.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28617.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28638.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28667.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28672.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28674.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28675.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28694.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28699.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28704.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28707.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28718.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28723.xdti_28hc_10t_30_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28726.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28767.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28779.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28803.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28829.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28839.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28877.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28882.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28884.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28924.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28927.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28928.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28965.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst28984.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29015.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29016.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29043.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29063.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29073.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29080.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29097.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29122.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29123.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29138.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29144.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29145.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29152.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29175.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29176.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29190.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29191.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29216.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29219.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29231.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29234.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29273.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29285.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29300.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29315.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29317.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29321.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29323.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29324.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29329.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29334.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29336.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29344.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29354.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29371.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29377.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29380.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29400.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29448.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29468.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29484.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29488.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29513.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29517.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29522.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29526.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29533.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29538.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29546.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29560.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29563.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29570.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29604.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29607.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29648.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29650.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29663.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29691.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29699.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29747.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29750.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29754.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29759.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29817.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29831.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29848.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29850.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29851.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29856.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29923.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29924.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29965.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29970.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29974.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29976.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29982.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst29996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30002.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30003.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30022.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30030.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30046.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30050.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30052.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30087.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30092.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30115.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30137.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30146.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30171.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30174.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30175.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30181.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30213.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30217.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30224.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30237.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30243.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30286.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30290.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30296.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30303.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30307.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30315.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30334.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30342.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30345.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30381.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30384.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30410.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30415.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30439.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30452.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30454.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30459.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30473.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30474.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30486.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30488.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30534.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30594.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30636.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30639.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30641.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30663.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30675.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30677.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30700.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30703.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30705.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30706.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30744.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30784.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30832.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30837.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30864.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30872.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30878.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30928.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30943.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30979.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30987.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30997.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst30999.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31041.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31067.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31069.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31080.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31122.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31123.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31145.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31157.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31169.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31188.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31197.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31214.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31228.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31233.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31288.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31300.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31307.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31347.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31362.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31381.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31397.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31409.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31418.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31426.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31430.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31459.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31497.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31505.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31547.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31553.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31566.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31602.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31605.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31628.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31631.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31659.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31664.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31699.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31702.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31704.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31733.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31750.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31770.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31801.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31826.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31833.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31859.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31886.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31916.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31927.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31930.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31931.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31940.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31941.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31956.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst31957.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32016.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32018.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32019.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32030.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32058.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32072.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32085.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32094.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32099.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32109.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32137.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32148.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32169.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32199.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32201.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32203.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32207.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32233.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32243.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32248.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32249.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32270.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32288.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32342.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32359.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32365.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32372.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32378.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32380.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32422.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32438.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32450.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32451.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32464.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32466.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32473.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32489.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32496.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32497.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32499.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32504.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32508.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32517.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32533.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32534.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32543.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32549.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32564.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32567.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32571.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32583.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32605.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32672.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32690.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32723.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32774.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32782.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32788.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32808.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32815.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32819.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32821.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32823.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32835.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32858.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32868.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32874.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32918.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32982.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32992.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst32999.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33014.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33029.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33036.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33042.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33049.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33055.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33066.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33069.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33079.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33085.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33107.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33110.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33117.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33139.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33148.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33160.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33169.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33201.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33209.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33219.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33224.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33236.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33271.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33279.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33287.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33288.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33297.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33321.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33325.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33346.xdti_28hc_10t_30_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33356.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33387.xdti_28hc_10t_30_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33420.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33446.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33487.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33497.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33502.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33517.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33551.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33556.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33594.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33606.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33663.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33674.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33690.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33713.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33751.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33765.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33768.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33779.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33803.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33815.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33825.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33829.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33851.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33879.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33899.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33901.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33929.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33930.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33934.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33946.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33964.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33979.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33980.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst33996.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34015.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34019.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34039.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34058.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34095.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34109.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34110.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34117.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34140.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34143.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34144.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_ctl31s2ckr2_jm.xinst34159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst84.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst272.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst432.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst509.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst547.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst976.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1561.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1654.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1693.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1733.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2190.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2318.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2491.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3320.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3355.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3470.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3586.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3614.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4000.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5249.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5259.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5820.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5864.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6211.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6548.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6692.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6947.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7288.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7386.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7413.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7431.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7534.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7568.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8409.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8415.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9399.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9551.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9865.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10781.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11637.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11734.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11799.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11818.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11845.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11937.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[0].xinst12342.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst84.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst272.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst432.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst509.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst547.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst976.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1561.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1654.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1693.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1733.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2190.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2318.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2491.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3320.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3355.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3470.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3586.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3614.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4000.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5249.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5259.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5360.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5820.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5864.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6211.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6504.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6548.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6692.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6947.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7288.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7386.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7413.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7431.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7534.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7568.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8409.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8415.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9399.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9551.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9865.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10146.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10781.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11637.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11734.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11799.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11818.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11845.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11937.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[1].xinst12342.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst84.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst272.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst432.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst509.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst547.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst976.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1561.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1654.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1693.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1733.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2190.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2318.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2491.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3320.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3355.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3470.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3586.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3614.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3765.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4000.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4827.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5249.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5259.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5360.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5820.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5864.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6211.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6504.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6548.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6692.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6947.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7288.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7386.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7413.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7431.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7568.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8409.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8415.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9185.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9399.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9551.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9865.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11637.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11734.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11799.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11818.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11845.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11937.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[2].xinst12342.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst84.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst272.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst432.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst509.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst547.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst976.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1561.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1654.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1733.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2190.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2318.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2491.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3320.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3355.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3470.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3586.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3614.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4000.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5188.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5249.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5259.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5820.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5864.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6211.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6504.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6548.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6692.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6947.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7288.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7386.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7413.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7431.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7534.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7568.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8409.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8415.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9399.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9551.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9865.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10146.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10781.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11637.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11734.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11799.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11818.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11845.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11937.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[3].xinst12342.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst84.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst272.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst432.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst509.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst547.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst976.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1561.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1654.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1733.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2190.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2318.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2491.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3320.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3355.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3470.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3586.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3614.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3765.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4000.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4827.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5188.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5249.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5259.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5360.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5820.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5864.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6211.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6504.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6548.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6692.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6947.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7288.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7386.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7413.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7431.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7534.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7568.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8409.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8415.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9185.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9399.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9551.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9865.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10146.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10781.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11637.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11734.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11799.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11818.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11845.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11937.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[4].xinst12342.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst84.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst272.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst432.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst509.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst547.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst976.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1561.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1654.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1733.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2190.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2318.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2491.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3320.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3355.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3470.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3586.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3614.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4000.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5188.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5249.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5259.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5820.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5864.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6211.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6504.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6548.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6692.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6947.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7288.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7386.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7413.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7431.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7568.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8409.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8415.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9399.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9551.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9865.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10146.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11637.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11734.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11799.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11818.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11845.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11937.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[5].xinst12342.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst84.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst272.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst432.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst509.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst547.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst976.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1561.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1654.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1733.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2190.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2318.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2491.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3320.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3355.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3470.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3586.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3614.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4000.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5249.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5259.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5820.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5864.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6211.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6504.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6548.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6692.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6947.xdti_28hc_10t_30_mux21 80.56 100.00 41.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7288.xdti_28hc_10t_30_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7386.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7413.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7431.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7534.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7568.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7728.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8409.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8415.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9399.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9551.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9865.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10781.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11637.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11734.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11799.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11818.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11845.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11858.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11937.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[6].xinst12342.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst23.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst26.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst27.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst28.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst30.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst39.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst59.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst74.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst75.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst84.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst90.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst91.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst96.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst98.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst102.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst105.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst112.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst116.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst121.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst128.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst129.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst133.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst141.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst146.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst159.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst165.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst172.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst184.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst194.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst201.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst204.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst209.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst246.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst272.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst273.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst277.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst282.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst286.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst293.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst304.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst308.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst309.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst344.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst363.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst381.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst403.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst415.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst423.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst426.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst432.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst434.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst445.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst453.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst460.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst484.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst502.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst509.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst514.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst524.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst532.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst542.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst544.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst547.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst553.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst592.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst596.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst601.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst605.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst635.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst636.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst651.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst666.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst668.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst673.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst693.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst705.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst708.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst711.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst750.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst755.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst761.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst771.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst778.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst785.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst793.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst798.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst803.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst804.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst810.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst859.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst861.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst893.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst906.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst914.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst923.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst927.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst945.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst949.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst950.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst951.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst952.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst12.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst47.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst48.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst53.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst62.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst74.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst79.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst82.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst88.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst96.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst97.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst169.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst184.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst210.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst241.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst260.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst272.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst285.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst333.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst339.xdti_28hc_10t_30_mux21 75.00 100.00 25.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst340.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst400.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst963.xinst413.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst968.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst976.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst977.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst978.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst981.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst998.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1002.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1011.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1024.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1038.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1065.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1081.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1085.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1096.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1119.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1121.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1136.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1149.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1161.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1162.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1168.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1194.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1202.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1221.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1229.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1237.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1242.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1250.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1254.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1257.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1259.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1313.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1317.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1339.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1341.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1343.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1352.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1364.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1368.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1389.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1400.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1407.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1414.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1418.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1425.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1427.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1437.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1452.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1483.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1504.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1510.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1518.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1556.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1561.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1590.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1595.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1596.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1603.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1606.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1628.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1637.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1650.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1651.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1654.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1675.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1678.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1680.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1681.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1687.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1702.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1704.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1712.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1715.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1717.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1719.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1733.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1763.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1768.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1774.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1781.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1792.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1797.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1799.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1806.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1842.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1856.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1866.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1886.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1891.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1904.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1922.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1928.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1931.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1935.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1936.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1940.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1943.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1962.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1964.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1981.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1986.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst1998.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2004.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2013.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2017.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2021.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2030.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2041.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2043.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2049.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2053.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2061.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2071.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2093.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2097.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2099.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2102.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2108.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2114.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2115.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2116.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2127.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2142.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2156.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2167.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2170.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2179.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2188.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2189.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2190.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2193.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2195.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2223.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2224.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2228.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2242.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2274.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2283.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2290.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2299.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2300.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2318.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2326.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2328.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2330.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2376.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2377.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2385.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2387.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2400.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2444.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2447.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2456.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2491.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2497.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2519.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2520.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2521.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2528.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2537.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2540.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2550.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2555.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2570.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2571.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2574.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2584.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2601.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2619.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2623.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2630.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2631.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2653.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2683.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2687.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2692.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2727.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2734.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2746.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2752.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2765.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2777.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2793.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2806.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2807.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2812.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2816.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2830.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2836.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2842.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2891.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2898.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2902.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2918.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2945.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2951.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2953.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2965.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2992.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2994.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst2999.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3002.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3004.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3007.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3044.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3057.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3061.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3063.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3068.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3098.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3105.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3118.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3119.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3147.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3149.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3156.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3171.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3187.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3217.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3229.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3241.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3244.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3251.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3252.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3258.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3260.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3266.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3291.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3310.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3311.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3317.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3318.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3319.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3320.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3323.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3326.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3348.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3355.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3369.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3370.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3375.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3376.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3381.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3402.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3404.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3407.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3408.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3417.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3426.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3428.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3435.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3437.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3458.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3470.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3479.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3487.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3489.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3492.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3495.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3537.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3545.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3557.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3559.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3565.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3586.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3593.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3598.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3599.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3601.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3614.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3622.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3632.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3677.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3681.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3685.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3688.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3711.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3719.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3729.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3734.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3750.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3764.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3765.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3774.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3775.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3781.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3819.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3822.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3836.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3840.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3863.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3872.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3873.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3875.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3881.xdti_28hc_10t_30_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3885.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3890.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3891.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3903.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3907.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3913.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3940.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3945.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3962.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3980.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst3996.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4000.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4020.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4082.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4083.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4085.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4099.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4100.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4132.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4147.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4205.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4226.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4232.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4239.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4256.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4280.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4283.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4287.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4291.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4315.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4331.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4333.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4337.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4340.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4345.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4351.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4367.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4379.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4402.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4410.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4433.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4435.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4449.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4462.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4465.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4477.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4490.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4493.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4495.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4498.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4501.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4509.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4511.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4528.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4536.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4540.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4546.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4547.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4561.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4565.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4579.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4588.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4595.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4600.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4611.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4614.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4622.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4630.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4644.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4657.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4660.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4678.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4680.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4683.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4684.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4686.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4724.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4726.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4760.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4768.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4789.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4791.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4804.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4808.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4809.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4812.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4825.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4847.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4852.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4853.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4879.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4906.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4917.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4925.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4931.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4937.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4941.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4957.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4973.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4992.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst4993.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5003.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5016.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5017.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5032.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5045.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5064.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5066.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5069.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5087.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5093.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5124.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5128.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5130.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5137.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5157.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5160.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5170.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5176.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5180.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5188.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5200.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5204.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5217.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5222.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5228.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5230.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5232.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5237.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5241.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5249.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5257.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5259.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5261.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5290.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5293.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5295.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5297.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5308.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5318.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5341.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5356.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5358.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5366.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5407.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5410.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5412.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5413.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5418.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5432.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5436.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5438.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5450.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5462.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5469.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5473.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5496.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5505.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5510.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5518.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5528.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5541.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5557.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5564.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5581.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5617.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5620.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5632.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5649.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5653.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5675.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5679.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5722.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5728.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5742.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5749.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5768.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5781.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5784.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5786.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5811.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5820.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5829.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5831.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5864.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5878.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5887.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5895.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5918.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5920.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5921.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5939.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5946.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5947.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5948.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5968.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5973.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5975.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst5993.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6006.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6011.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6020.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6022.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6024.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6025.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6027.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6036.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6053.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6074.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6079.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6080.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6081.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6082.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6083.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6092.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6101.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6122.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6126.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6133.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6145.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6150.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6157.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6168.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6170.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6182.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6184.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6185.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6192.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6202.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6206.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6210.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6211.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6224.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6226.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6241.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6253.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6276.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6280.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6282.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6297.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6320.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6324.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6337.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6348.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6358.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6365.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6374.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6375.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6379.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6386.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6387.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6391.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6405.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6410.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6416.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6418.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6425.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6441.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6451.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6460.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6474.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6475.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6486.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6494.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6504.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6505.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6518.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6519.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6521.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6534.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6538.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6548.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6554.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6557.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6572.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6578.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6579.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6580.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6583.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6586.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6587.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6626.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6635.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6640.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6644.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6654.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6656.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6663.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6667.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6699.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6706.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6707.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6717.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6728.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6736.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6738.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6744.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6745.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6777.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6789.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6823.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6837.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6838.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6839.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6841.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6843.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6850.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6857.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6897.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6899.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6905.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6910.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6911.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6917.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6918.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6929.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6947.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6954.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6977.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6982.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6997.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst6999.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7042.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7052.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7054.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7055.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7064.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7086.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7089.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7091.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7099.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7101.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7107.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7118.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7123.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7124.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7125.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7128.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7134.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7163.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7173.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7174.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7177.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7178.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7196.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7198.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7240.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7261.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7286.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7288.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7289.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7301.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7314.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7325.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7360.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7386.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7389.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7399.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7401.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7413.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7418.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7429.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7431.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7432.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7434.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7439.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7460.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7471.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7476.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7477.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7480.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7484.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7495.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7503.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7516.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7534.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7541.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7564.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7568.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7573.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7584.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7600.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7603.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7606.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7610.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7615.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7625.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7627.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7629.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7633.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7646.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7648.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7668.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7674.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7689.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7693.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7703.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7704.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7723.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7726.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7727.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7728.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7767.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7780.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7787.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7795.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7796.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7805.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7806.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7810.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7811.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7813.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7814.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7818.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7826.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7858.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7859.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7887.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7897.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7898.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7899.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7904.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7906.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7911.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7920.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7922.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7940.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7964.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7968.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7969.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7971.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7974.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7989.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst7993.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8001.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8002.xdti_28hc_10t_30_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8017.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8034.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8043.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8045.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8055.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8059.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8065.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8066.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8070.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8074.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8083.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8108.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8116.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8134.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8135.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8138.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8139.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8151.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8158.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8164.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8174.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8182.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8191.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8212.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8225.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8230.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8236.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8238.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8245.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8248.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8255.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8271.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8288.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8330.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8332.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8335.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8341.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8343.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8345.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8350.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8371.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8380.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8391.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8409.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8415.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8452.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8464.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8466.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8469.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8477.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8491.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8494.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8514.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8520.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8521.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8545.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8559.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8560.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8574.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8575.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8577.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8591.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8618.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8629.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8636.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8640.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8641.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8647.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8656.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8666.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8696.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8715.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8729.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8740.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8742.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8746.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8753.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8755.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8758.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8772.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8775.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8776.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8779.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8787.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8795.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8808.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8817.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8819.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8823.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8832.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8841.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8845.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8873.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8900.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8909.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8911.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8912.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8920.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8926.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8929.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8932.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8933.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8951.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8955.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8959.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8960.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8975.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8985.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst8990.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9001.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9023.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9031.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9034.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9037.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9038.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9054.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9068.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9079.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9084.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9118.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9122.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9132.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9142.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9145.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9149.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9156.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9158.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9166.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9185.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9188.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9189.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9198.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9199.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9205.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9213.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9242.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9248.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9276.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9298.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9310.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9322.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9327.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9330.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9351.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9352.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9353.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9366.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9384.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9385.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9397.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9399.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9417.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9420.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9422.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9441.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9445.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9448.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9455.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9457.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9462.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9463.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9485.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9488.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9499.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9500.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9504.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9506.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9525.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9529.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9551.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9573.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9596.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9600.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9606.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9616.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9619.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9635.xdti_28hc_10t_30_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9650.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9652.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9660.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9665.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9668.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9678.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9685.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9688.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9690.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9691.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9692.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9714.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9717.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9722.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9728.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9737.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9740.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9752.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9762.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9772.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9777.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9796.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9797.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9812.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9828.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9852.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9862.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9863.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9865.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9874.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9875.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9879.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9908.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9925.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9930.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9944.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9954.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9964.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9968.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst9989.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10010.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10012.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10013.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10024.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10031.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10035.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10038.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10045.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10048.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10056.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10057.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10063.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10071.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10073.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10083.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10098.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10119.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10120.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10123.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10131.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10136.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10140.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10146.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10153.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10162.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10166.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10174.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10175.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10177.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10184.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10190.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10191.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10193.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10197.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10200.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10201.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10215.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10219.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10235.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10239.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10243.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10250.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10251.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10264.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10275.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10279.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10283.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10288.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10294.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10297.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10306.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10334.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10335.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10343.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10346.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10347.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10355.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10358.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10368.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10376.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10382.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10390.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10394.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10396.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10398.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10416.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10421.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10431.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10437.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10444.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10447.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10456.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10467.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10476.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10512.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10538.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10556.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10560.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10567.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10583.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10589.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10606.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10612.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10628.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10634.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10644.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10647.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10648.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10649.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10655.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10658.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10683.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10695.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10710.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10725.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10740.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10747.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10781.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10786.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10791.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10797.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10802.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10805.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10824.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10827.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10838.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10839.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10855.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10870.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10898.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10918.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10920.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10924.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10938.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10942.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10950.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10953.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10959.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10962.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10969.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10971.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10983.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst10993.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11004.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11010.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11016.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11033.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11044.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11062.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11093.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11096.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11098.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11100.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11106.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11111.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11113.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11130.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11143.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11154.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11155.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11159.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11179.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11191.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11193.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11195.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11209.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11227.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11230.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11234.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11246.xdti_28hc_10t_30_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11247.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11253.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11258.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11261.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11265.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11266.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11269.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11277.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11281.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11302.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11307.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11341.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11344.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11348.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11370.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11379.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11380.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11382.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11383.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11386.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11389.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11402.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11405.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11408.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11425.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11439.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11447.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11458.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11472.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11485.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11493.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11494.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11506.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11507.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11510.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11522.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11532.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11536.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11537.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11539.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11543.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11545.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11546.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11570.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11571.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11578.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11579.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11586.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11587.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11599.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11637.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11640.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11643.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11645.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11653.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11659.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11665.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11670.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11681.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11702.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11721.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11723.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11734.xdti_28hc_10t_30_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11755.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11757.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11763.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11783.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11792.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11796.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11799.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11801.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11813.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11814.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11818.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11820.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11833.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11835.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11837.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11845.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11855.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11856.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11857.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11858.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11866.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11880.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11883.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11884.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11903.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11919.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11925.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11937.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11944.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11955.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11967.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11982.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11986.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst11990.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12000.xdti_28hc_10t_30_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12008.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12010.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12018.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12019.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12034.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12053.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12066.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12068.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12088.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12095.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12097.xdti_28hc_10t_30_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12117.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12119.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12127.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12141.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12151.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12158.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12160.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12173.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12176.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12185.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12187.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12199.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12206.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12209.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12210.xdti_28hc_10t_30_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12214.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12217.xdti_28hc_10t_30_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12218.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12227.xdti_28hc_10t_30_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12244.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12253.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12264.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12265.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12268.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12293.xdti_28hc_10t_30_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12300.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12301.xdti_28hc_10t_30_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12302.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12312.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12314.xdti_28hc_10t_30_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12331.xdti_28hc_10t_30_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm28hpcp_ddr4_phy.dti_tm28hpcpd4r2_18d_dq8_jm[7].xinst12342.xdti_28hc_10t_30_mux21 88.89 100.00 66.67 100.00

Cond Coverage for Module : dti_mux21
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       363908
 EXPRESSION (S ? D1 : D0)
             1
-1-Status
0Covered
1Covered
Toggle Coverage for Module : dti_mux21
TotalCoveredPercent
Totals 6 4 66.67
Total Bits 12 8 66.67
Total Bits 0->1 6 4 66.67
Total Bits 1->0 6 4 66.67

Ports 6 4 66.67
Port Bits 12 8 66.67
Port Bits 0->1 6 4 66.67
Port Bits 1->0 6 4 66.67

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
VDD No No No INPUT
VSS No No No INPUT
Z Yes Yes Yes OUTPUT
D0 Yes Yes Yes INPUT
D1 Yes Yes Yes INPUT
S Yes Yes Yes INPUT

Branch Coverage for Module : dti_mux21
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 363908 2 2 100.00 



363908     assign Z = S ? D1 : D0;
                        -1-  
                        ==>  
                        ==>

Branches:
-1-Status
1 Covered
0 Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%